Circuit Analysis Tools (CAT)

Program Manager

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Program Information

IARPA Day Poster

The semiconductor industry continues to scale integrated circuits in accordance with Moore's law, and is currently developing the processing and design infrastructure at the 22 nm technology node and beyond. However, analysis tools, instrumentation, and methods have not kept pace with the need for improved analytical capability and metrology of these complex circuits. To ensure that the government’s capabilities keep pace with Moore’s Law, the Circuit Analysis Tools (CAT) program is developing tools and techniques that are necessary for circuit analysis at future technology nodes, specifically, at 22 nm and beyond. This also includes analysis tools capable of working with the advanced packaging of circuits at these nodes including, but not limited to, stacked die and integrated 3-dimensional ICs. The program is divided into four thrust areas: circuit edit, fault isolation, logic analysis, and fast imaging, with each area having some goals associated with sample preparation. The development tasks for each of these thrusts will focus on developing an analysis tool as a laboratory platform to demonstrate capability at the 22 nm node in Phase 1, and building and optimizing a prototype tool to demonstrate capability at the 11 nm node in Phase 2.

Performers (Prime Contractors)

Boston University; Carl Zeiss SMT, Inc.; DCG Systems, Inc.; HRL Laboratories, LLC; JHT Instruments, LLC; Neocera, Inc.; University of Maryland; Varioscale, Inc.

Research Area(s)

  • Cybersecurity & information assurance
  • Hardware assurance
  • Microelectronics

Related Publications

To access CAT program-related publications, please visit Google Scholar.

Related Article(s)