Trusted Integrated Chips (TIC)

Recent developments in the semiconductor industry show tremendous opportunity for the realization of integrated circuits and systems-on-a-chip derived from state-of-the art foundry processes. The ability of semiconductor foundries to realize multiple types of integrated circuits, MEMS, and other More-Than-Moore capabilities will likely continue in the future. In particular, such foundry processes are not only demonstrating exceptionally high performance in several technology areas, but also demonstrating low-cost, fast turn-around time, and high yield. In addition to maintaining our supply and access to integrated circuits derived from the U.S. Trusted Foundry, it is important for both the Intelligence Community and other government agencies to have access to other state-of-the art manufacturing capabilities derived from world foundries with assurance that such chips are safe and secure without malicious circuitry or reliability concerns. In addition, the protection of design intent and systems performance is an important goal to be realized in TIC.

The TIC Program aims to develop new approaches to chip fabrication where security and intellectual property concerns would otherwise prohibit the use of off-shore manufacturing foundries. Specifically, TIC seeks to address secure foundry manufacturing of chips in several ways:

  1. Development of split-manufacturing processes in which a Front-End-of Line (FEOL) process defines transistor building blocks up to the point of the first or second metallization followed by a Back-End-of-Line (BEOL) process in which remaining metallizations are carried out in secure trusted facilities in the U.S. Initially, the logistics and compatibility of using more than one fabrication facility at the 130 nm node will be of concern.
  2. Chip obfuscation methods whereby the intent of digital and analog functions and their associated building blocks are disguised in their function within the FEOL process.
  3. New verification methods that ensure that no malicious circuitry has been added during fabrication. New ideas that are different from those being explored in other federal research programs, such as DARPA's TRUST and IRIS programs, are encouraged.
  4. New approaches to 3-D fabrication at significant semiconductor manufacturing nodes. This includes new transistor/circuit designs and creative stacking methods such as those which may be required for integrated MEMS and III-V-on-Si chips.

It is anticipated that the TIC Program will logically scale its capabilities over a four year period having started with a core 130 nm-node capability and subsequently moving toward a 22 nm capability at the end of a four year period. It is expected that methodologies to be demonstrated will define both high-performance integrated circuits and integrated systems such as MEMS over the next 10 years.

If successful, the TIC Program will have demonstrated a new ability for both the U.S. government and industry to realize safe and secure integrated chips having protected functional goals and proprietary circuit designs. Collaborative efforts and teaming among potential performers will be strongly encouraged. It is anticipated that teams will be multidisciplinary with capabilities including: circuit design, chip manufacturing, and characterization.

IARPA anticipates that universities and companies from around the world will participate in this program.

For information contact:

dni-iarpa-info@iarpa.gov

 

Solicitation Status: Closed

IARPA-BAA-11-09
Proposers' Day Date: July 27, 2011
BAA Release Date: October 26, 2011

Addtional Information

Proposers' Day Briefing