Trusted Integrated Chips (TIC)

The Intelligence Advanced Research Projects Activity (IARPA) will host a Proposers' Day Conference for the Trusted Integrated Chips (TIC) Program on July 27, 2011 in anticipation of the release of a new solicitation in support of the program. The Conference will be held from 8:30 am to 3:30 pm in the Washington, D.C., metropolitan area. The purpose of the conference will be to provide information on the TIC Program, to address questions from potential proposers, and to provide a forum for potential proposers to present their capabilities for teaming opportunities.

This announcement serves as a pre-solicitation notice and is issued solely for information and planning purposes. The Proposers' Day Conference does not constitute a formal solicitation for proposals or proposal abstracts. Conference attendance is voluntary and is not required to propose to future solicitations (if any) associated with this program.

Program Description and Goals

Recent developments in the semiconductor industry show tremendous opportunity for the realization of integrated circuits and systems-on-a-chip derived from state-of-the art foundry processes. The ability of semiconductor foundries to realize multiple types of integrated circuits, MEMS, and other More-Than-Moore capabilities will likely continue in the future. In particular, such foundry processes are not only demonstrating exceptionally high performance in several technology areas, but also demonstrating low-cost, fast turn-around time, and high yield. In addition to maintaining our supply and access to integrated circuits derived from the U.S. Trusted Foundry, it is important for both the Intelligence Community and other government agencies to have access to other state-of-the art manufacturing capabilities derived from world foundries with assurance that such chips are safe and secure without malicious circuitry or reliability concerns. In addition, the protection of design intent and systems performance is an important goal to be realized in TIC.

The TIC Program aims to develop new approaches to chip fabrication where security and intellectual property concerns would otherwise prohibit the use of off-shore manufacturing foundries. Specifically, TIC seeks to address secure foundry manufacturing of chips in several ways:

  1. Development of split-manufacturing processes in which a Front-End-of Line (FEOL) process defines transistor building blocks up to the point of the first or second metallization followed by a Back-End-of-Line (BEOL) process in which remaining metallizations are carried out in secure trusted facilities in the U.S. Initially, the logistics and compatibility of using more than one fabrication facility at the 130 nm node will be of concern.
  2. Chip obfuscation methods whereby the intent of digital and analog functions and their associated building blocks are disguised in their function within the FEOL process.
  3. New verification methods that ensure that no malicious circuitry has been added during fabrication. New ideas that are different from those being explored in other federal research programs, such as DARPA's TRUST and IRIS programs, are encouraged.
  4. New approaches to 3-D fabrication at significant semiconductor manufacturing nodes. This includes new transistor/circuit designs and creative stacking methods such as those which may be required for integrated MEMS and III-V-on-Si chips.

It is anticipated that the TIC Program will logically scale its capabilities over a four year period having started with a core 130 nm-node capability and subsequently moving toward a 22 nm capability at the end of a four year period. It is expected that methodologies to be demonstrated will define both high-performance integrated circuits and integrated systems such as MEMS over the next 10 years.

If successful, the TIC Program will have demonstrated a new ability for both the U.S. government and industry to realize safe and secure integrated chips having protected functional goals and proprietary circuit designs. Collaborative efforts and teaming among potential performers will be strongly encouraged. It is anticipated that teams will be multidisciplinary with capabilities including: circuit design, chip manufacturing, and characterization.

IARPA anticipates that universities and companies from around the world will participate in this program.

Registration Information

Attendees must register no later than 5:00pm Eastern July 20, 2011 at Directions to the conference facility and other materials will be available on that website. No walk-in registrations will be allowed.

Due to space limitations, attendance will be limited to the first 140 registrants and to no more than 2 representatives per organization. All attendees will be required to present a government-issued photo identification to enter the conference. Non-US citizens will be required to submit a visit request form for Foreign Nationals at least 5 business days prior to the conference. The form and submission instructions can be found on the registration website.

Additional Information

Attendees who wish to present organization capabilities for potential teaming opportunities may request to do so by sending an e-mail along with their presentation to Presentations will be limited to 10 minutes with a maximum of 5 slides (MS PowerPoint or PDF format). Opportunities to present will be limited by time and will therefore be on a first-to-ask basis. Deadline for requests is close of business (5:00pm Eastern) July 18, 2011. It is the presenter's responsibility to ensure that all materials briefed are appropriately marked and approved for presentation by their organization. The IARPA Point of Contact will review and approve all presentations.

This Proposers' Day is intended for participants who are eligible to compete on the anticipated BAA. Other Government Agencies, Federally Funded Research and Development Centers (FFRDCs), and University Affiliated Research Centers (UARCs) will not be eligible to submit proposals to the anticipated BAA nor participate as team members under proposals submitted by eligible entities. While such entities are not prohibited from attending the Proposers' Day, due to space limitations, preference will be given first to those organizations that are eligible to compete.

IARPA will not provide reimbursement for costs incurred to participate in this conference.

Attendees must register no later than 5:00pm Eastern July 20, 2011 at


For information contact:


Solicitation Status: Closed

Proposers' Day Date: July 27, 2011
BAA Release Date: October 26, 2011

Addtional Information

Proposers' Day Briefing