Rapid Analysis of Various Emerging Nanoelectronics (RAVEN)

Between 2011 and 2015, the semiconductor industry saw significant advances in both the scaling of integrated circuits and 3-D integration of multiple wafers, monolithically grown stacked circuits, and non-CMOS structures. Multiple flash memory manufacturers are fabricating 16+ stacked chips for memory and logic-in-memory applications. In addition, 2.5 D circuits mounted on an interposer die have become an industry standard.  High-yield manufacturing of these structures will require unique capabilities for process verification and failure analysis.

Similarly, in keeping with Moore’s Law scaling, 14 nm microprocessors have been in production since July 2014 and 7 nm circuits were demonstrated at Albany Nanotech in early 2015.[1]   Samsung Corporation, Taiwan Semiconductor Manufacturing Company (TSMC), and GlobalFoundries have announced plans to ship production-quality 10 nm integrated circuits in late 2016[2], Intel plans to ship 10 nm integrated circuits in 2017[3], and TSMC plans to offer 7 nm chips in 2017. [4] Manufacturing at these technology nodes will require high-speed and high-resolution image acquisition for process verification and failure analysis.

The RAVEN program is focused on developing an analysis tool capable of imaging minimum size circuit features on a silicon integrated circuit chip. The features of interest include metal, polysilicon, vias, contacts, shallow trench isolation (STI) regions, and dielectrics. The ability to image n- and p-wells is desired but not required. Possible tool approaches may include but are not limited to x-ray based microscopes, high brightness scanning electron systems, multi-beam scanning electron microscopes, non-scanned projected image electron systems, ion beam imaging systems, ultra-high resolution interference optical microscopes, and multiple array AFM systems. The program is also interested in sample preparation innovations relevant to specific techniques, and novel approaches to image reconstruction for 2-D and 3-D devices.

Contracting Office Address

Office of the Director of National Intelligence
Intelligence Advanced Research Projects Activity
Washington, DC 20511

Primary Point of Contact

Carl McCants
Program Manager
dni-iarpa-baa-15-12@iarpa.gov

References


http://www-03.ibm.com/press/us/en/pressrelease/47301.wss.

http://www.eetimes.com/document.asp?doc_id=1328272.

http://www.extremetech.com/computing/210050-intel-confirms-10nm-delayed-to-2017-will-introduce-kaby-lake-at-14nm-to-fill-gap.

http://www.tsmc.com/english/dedicatedFoundry/technology/future_rd.htm.

Solicitation Status: CLOSED

IARPA-BAA-15-12

Proposers' Day Date: August 25, 2015
BAA Release Date: January 12, 2016
BAA Question Period:
January 12, 2016 – February 16, 2016
Proposal Due Date: March 14, 2016

Additional Information

Proposers' Day Briefings

RAVEN Proposers' Day Briefing