Circuit Analysis Tools (CAT)
The semiconductor electronics industry continues to scale in accordance with Moore's law, and is currently developing the processing and design infrastructure to realize the 22 nm technology node and beyond. However, analysis tools, instrumentation, and methods have not kept pace with the need for improved analytical capability.
Numerous challenges arise in the wake of such rapid progress. Complex circuits with rapidly decreasing critical dimensions will have die-level visual and non-visual defects at the nano- and atomic-scale, which will demand increased resolution in tools that are able to analyze areas as large as 10 microns to find these defects. Increasing numbers of transistors require more levels of metal interconnect (approaching 12 by the 22 nm node), which further complicates fault isolation, circuit edit and analysis techniques. In many cases, the only access to the transistors is through the back-side of the silicon, which requires extensive sample preparation and the need to work with creative approaches from both front- and back-side to test individual transistors. In some cases it will be necessary to advance or develop entirely new techniques to address nano-scale analysis at a comparatively large working distance and through intervening materials. Advanced packaging solutions to address the problem of increasing power dissipation and integration will require new back-side and through-packaging fault isolation approaches. The test time and hence the cost will become prohibitive with the increasing density and complexity of the logic chips.
IARPA is interested in tools that are necessary for circuit analysis at future technology nodes, specifically, the 22 nm node and beyond. This also includes analysis tools capable of working with the advanced packaging of circuits at these advanced technology nodes including but not limited to stacked die. These tools are required to evaluate commercial products for use by the Government. IARPA is specifically interested in both global and local analysis tools and techniques that can address circuit edit, fault isolation, logic analysis and imaging challenges for which there are currently no solutions. This is analogous to the "red" boxes for technology issues in the International Technology Roadmap for Semiconductors (ITRS) annual reports, which can be found at www.itrs.net. We invite proposals to address challenges for which existing techniques have no clear evolutionary path to the 22 nm node and beyond. IARPA is looking for significant improvements in tool technology, including revolutionary tools and techniques that will enable electrical and physical measurements on future integrated circuits.
For information contact:
Solicitation Status: Closed
BAA Release Date: September 3, 2009
BAA Question Period: September 3, 2009 - December 1, 2009
White Paper Due Date: October 2, 2009
Proposal Due Date: December 11, 2009