IARPA: Intelligence Advanced Research Projects Activity

SYNOPSIS

The semiconductor industry has been advancing rapidly with aggressive scaling. Extending beyond the Moore’s Law of digital processing and storage integrated circuits, this scaling has extended to 3-dimensions to keep pace. This scaling trend has fostered the integration of diverse analog and digital components to provide high value systems such as sensors, actuators, and biochips. The key capabilities to fabricate the high performance integrated circuit components for these high value systems are in the commercial foundries, which now dominate the world’s production of high performance integrated circuits. It is desirable for the US academic community and the US industrial base to have open and assured access to obtain the highest performance integrated circuits (IC’s) and systems-on-chips (SoC’s) while ensuring that components have been securely fabricated according to design and that intellectual property is protected.

The goal of the TIC Program is to develop and demonstrate new split-manufacturing to chip fabrication where security and intellectual property protection can be assured. In split-manufacturing, the fabrication is divided into Front-End-of-Line (FEOL) consisting of transistor layers to be fabricated by offshore foundries and Back-End-of-Line (BEOL) consisting of metallizations to be fabricated by trusted US facilities. In this approach, the design intention is not disclosed to the FEOL fabricators. The development and demonstration of split-manufacturing will start at the 130 nm technology node in Phase 1. It is anticipated that the TIC Program performers will scale the development of their capabilities to the 22 nm node at the end of a five year period in Phase 3. The Government will offer the performers foundry services for FEOL and BEOL via dedicated Multi-Project Wafer (MPW) fabrication runs of the selected foundry technologies through Metal Oxide Semiconductor Implementation System (MOSIS). TIC Program performers will be able to use these foundry technologies for their design applications.

IARPA’s TIC Program seeks innovative concepts in the demonstration of the split-manufacturing concept applied to high performance chips (e.g., IC’s, SoC’s, and/or 3D IC’s). Offerors may propose to demonstrate the split-manufacturing concept in any of the following design applications:

• Mixed Signal
• Photonics-CMOS
• MEMS-CMOS
• Power-CMOS
• RF CMOS
• Memory-CMOS
• Josephson Junctions-CMOS
• Other systems integrated with CMOS

Contracting Office Address:
Office of the Director of National Intelligence
Intelligence Advanced Research Projects Activity
Washington, District of Columbia 20511
United States

Primary Point of Contact:
Dr. Dennis Polla
Program Manager
dni-iarpa-baa-11-09@ugov.gov

• IARPA-BAA-11-09 with all Supporting Documents
• IARPA-BAA-11-09 Questions and Answers
• Amendment 1

Proposers' Day Briefing

• TIC Proposers' Day Agenda
• TIC Proposers' Day Brief